Evaluation circuit for a DRAM

ABSTRACT

A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

BACKGROUND OF THE INVENTION

[0001] Field of the Invention

[0002] The invention relates to an evaluation circuit for evaluating theelectrical charge of a memory cell and to a memory device having such anevaluation circuit.

[0003] Dynamic random access memories (DRAMs) include a plurality ofmemory cells which each include a storage capacitor and a selectiontransistor. These memory cells are addressed via word and bit lineswhich are provided as columns and rows. A memory cell is written to bycharging the associated storage capacitor of the memory cell with anelectrical charge corresponding to the respective binary data unit.

[0004] During a read-out operation, the stored charge is then read outand amplified by an evaluation circuit connected to the bit line of thememory cell and the electrical potential of the bit line is comparedwith the electrical potential of an associated reference line. Dependingon the potential difference, the two electrical potentials are amplifiedto two predetermined potential values, the higher potential of the twolines generally being pulled to the potential of the supply voltage andthe lower potential being pulled to the ground potential.

[0005] The storage capacitor loses its charge over time due to leakagecurrents within the memory cell. For this reason, the charge of a memorycell must continually be refreshed again by reading and rewriting atshort time intervals.

[0006] The signals in large scale integrated memory cell configurationsare exposed to numerous interference sources in particular within thebit lines which connect the memory cells to the evaluation circuits. Inthis case, primarily a coupling capacitance between bit lines runningparallel to one another occurs as an interference factor. The electricalpotential of a bit line is influenced by the electrical potentials ofadjacent bit lines. The temporal fluctuation of this parasitic couplingsignal causes a noise which is referred to as coupling noise and, onaccount of superposition with the actual signal, has an interferingeffect during the read-out of the memory cell.

[0007] The decreasing distances—as a result of miniaturization—betweenadjacent bit lines of a large scale integrated memory cell configurationmean that the coupling capacitance between the bit lines rises, so thatit often exceeds the capacitance of the memory cells by a multiple inthe case of today's memory configurations. The coupling noise thenreaches the order of magnitude of the actual signals, so that, in anunfavorable case, the actual charge state of the storage capacitor maybe misinterpreted by the evaluation circuit.

[0008] In order to increase the reliability of such memory devices, itis therefore primarily attempted to reduce the coupling capacitances ofthe bit lines between the evaluation circuits and the memory cells. Abit line with reduced coupling capacitance has a more favorablesignal-to-noise ratio, which is in turn manifested in the reduction ofthe error rate in the interpretation of the memory cell information.

[0009] The continuous trend toward ever higher storage densitiesnecessitates further measures, however. In particular, it is found thatfurther, hitherto largely unknown interference factors also play a partin the error rate of the information evaluation of the memory cells.

SUMMARY OF THE INVENTION

[0010] It is accordingly an object of the invention to provide a memorydevice which overcomes the above-mentioned disadvantages of theheretofore-known memory devices of this general type and which reducesthe coupling capacitances of the signal lines within a memory cellconfiguration and which has a minimal error rate in the evaluation ofthe memory cell information.

[0011] With the foregoing and other objects in view there is provided,in accordance with the invention, a memory device, including:

[0012] a memory cell;

[0013] an evaluation circuit;

[0014] a reference line connected to the evaluation circuit

[0015] a bit line defining a bit line direction;

[0016] the memory cell being connected to the evaluation circuit via thebit line;

[0017] a first signal line, the bit line being connected, within theevaluation circuit, to the first signal line;

[0018] a second signal line, the reference line being connected, withinthe evaluation circuit, to the second signal line;

[0019] the bit line and the reference line having respective electricalpotentials, the evaluation circuit amplifying a difference between therespective electrical potentials of the bit line and the reference line;and

[0020] the first and second signal lines having a crossover regionwithin the evaluation circuit, the crossover region forming sectionsalong the bit line direction in the evaluation circuit, the sectionsalong the bit line direction having mutually substantially correspondingcapacitances.

[0021] In other words, a memory device having a memory cell and anevaluation circuit is provided, the memory cell being connected to theevaluation circuit via a bit line, and a reference line being connectedto the evaluation circuit, within the evaluation circuit the bit linebeing connected to a first signal line and the reference line beingconnected to a second signal line, and the evaluation circuit amplifyingthe difference between the electrical potentials of the bit line and thereference line, wherein the first and second signal lines have, withinthe evaluation circuit, a crossover region, the capacitances of thesections of the evaluation circuit which are formed by the crossoverregion in the bit line direction essentially mutually correspond to oneanother.

[0022] According to another feature of the invention, the first andsecond signal lines extend through the evaluation circuit; theevaluation circuit has two sides, the bit line and the reference linemake contact with a respective one of the first signal line and thesecond signal line at the two sides of the evaluation circuit; and thebit line is connected to the memory cell on a first one of the two sidesof the evaluation circuit and is connected to a further memory cell on asecond one of the two sides of the evaluation circuit.

[0023] According to yet another feature of the invention, the evaluationcircuit has a high-resistance input region for each of the bit line andthe reference line.

[0024] According to another feature of the invention, the evaluationcircuit is a measurement amplifier or a sense amplifier; and theamplifier amplifies the respective electrical potentials of the bit lineand of the reference line in accordance with the difference between therespective electrical potentials such that the respective electricalpotentials are amplified to two given potential values.

[0025] According to a further feature of the invention, the referenceline is configured as a bit line for a further memory cell.

[0026] According to another feature of the invention, the memory cell isa dynamic random access memory cell.

[0027] According to yet another feature of the invention, the sectionsformed by the crossover region along the bit line direction havecapacitances that substantially compensate one another.

[0028] According to another feature of the invention, a plurality ofevaluation circuits is disposed as a matrix configuration; a pluralityof memory cells is disposed between two evaluation circuits along thebit line; and the evaluation circuits are configured such that, in theword line direction, respective ones of the first and second signallines form respective crossover regions in every other one of theevaluation circuits.

[0029] It has been found that, in particular, the parallel signal lineswithin an evaluation circuit which are connected to a bit line and anassociated reference line also have interfering coupling capacitances.In this case, the resultant coupling noise can likewise lead tomisinterpretations of the charge state of the associated storagecapacitor and thus to read errors.

[0030] According to the invention, therefore, the first and secondsignal lines have, within the evaluation circuit, at least one crossoverregion which subdivides the evaluation circuit along the bit linedirection into at least two sections whose coupling capacitancesmutually compensate for one another. The signal lines of the evaluationcircuit preferably have exactly one crossover region which is arrangedexactly in the capacitive mid point of the evaluation circuit, so that,on account of the position change of the signal lines of the twosections, the potential difference coupled from an adjacent line intoone of the two sections has the same magnitude but an opposite sign.This makes it possible to minimize the coupling noise within theevaluation circuit.

[0031] In a further advantageous embodiment of the invention, the inputregions of the evaluation circuit for the bit line and the referenceline are high-impedance input regions. As a result, the evaluationcircuit does not “perceive” the coupling noise outside the evaluationcircuit, i.e. on the bit line and the reference line, and can thereforebe regarded practically as decoupled from the lines for the short timeperiod of the evaluation. Consequently, the parasitic couplingcapacitance can be largely compensated solely by the crossover region ofthe lines within the evaluation circuit in accordance with theinvention. In addition to the reduction of the error rate, the speed ofthe evaluation operation can thus also be increased again, whichbenefits the access speed in the memory.

[0032] In a further advantageous embodiment of the invention, theevaluation circuits are arranged in rows and columns. Since thecapacitance of two lines behaves reciprocally with respect to thedistance between the lines, the coupling capacitances of the signallines of two evaluation circuits that are not directly adjacent make asignificantly smaller contribution to the coupling noise than thedirectly adjacent signal lines. Therefore, it generally suffices toform, in accordance with the invention, the crossover of the signallines in every second evaluation circuit along the word line.

[0033] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0034] Although the invention is illustrated and described herein asembodied in an evaluation circuit for a DRAM, it is nevertheless notintended to be limited to the details shown, since various modificationsand structural changes may be made therein without departing from thespirit of the invention and within the scope and range of equivalents ofthe claims.

[0035] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036]FIG. 1 is a schematic circuit diagram of a configuration ofevaluation circuits according to the invention in a dynamic randomaccess memory; and

[0037]FIG. 2 is a detailed circuit diagram of two evaluationcircuits—adjacent in the word line direction—of the configurationaccording to the invention with crossed signal lines within one of theevaluation circuits.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Referring now to the figures of the drawings in detail the memorydevice according to the invention is illustrated using the example of aDRAM memory with bidirectional differential sense amplifiers, in whichthe sense amplifier has a differential bit line pair that makes contacton both sides (bit line shared sense amplifier). However, the crossoverof the signal lines within one sense amplifier according to theinvention, can also be applied to sense amplifiers which arecontact-connected on one side, and which are formed e.g. at the edge ofa regular configuration of memory devices, and also other known circuitsfor the read-out of memory cells. Furthermore, the invention is not justlimited to DRAM memories, but also includes other memory elements inwhich evaluation circuits of the abovementioned type are used toevaluate the memory cell information.

[0039]FIG. 1 shows a detail from a regular configuration of memorydevices of a DRAM memory with six sense or measurement amplifiersSA1-SA6 and eight bit lines BL1-BL4, BL1-BL4, the sense amplifiers SA1,SA3, SA5 being arranged in a first row and the sense amplifiers SA2,SA4, SA6 being arranged in a second row along the bit line direction.

[0040] A plurality of word lines WL, {overscore (WL)} run between thesense amplifiers SA1-SA6 arranged in the bit line direction, a memorycell MC, {overscore (MC)} including a storage capacitor and transfertransistor in each case being formed in the crossover regions betweenthe word lines and the bit lines BL1-BL4, {overscore (BL)}1-{overscore(BL)}4. In this case, the memory cells MC are preferably arranged in thecrossover regions between in each case one of the word lines WL and oneof the bit lines BL of a bit line pair and the memory cells {overscore(MC)} are arranged in the crosssover regions between a word line{overscore (WL)} adjacent to the word line WL and the other bit line{overscore (BL)} of a bit line pair.

[0041] For the sake of clarity, FIG. 1 only illustrates two word linesWL1, {overscore (WL)}1 and eight memory cells MC1-MC4, {overscore(MC)}1-{overscore (MC)}4 between the sense amplifiers SA1, SA3 and SA2,SA4. The memory cells MC between the sense amplifiers SA1, SA5 and SA2,SA6 are arranged according to the same scheme in the exemplaryembodiment illustrated here.

[0042] The sense amplifiers SA1, SA2 are configured bidirectional, thesignal lines SL1, {overscore (SL)}1, SL2, {overscore (SL)}2 formedwithin the sense amplifiers SA1, SA2, the course of which signal linesis shown simplified in FIG. 1, being contact-connected by in each casetwo bit lines BL1, {overscore (BL)}1, and BL2, {overscore (BL)}2,forming a pair, at both sides of the sense amplifiers SA1, SA2. Sincethe internal circuitry of the sense amplifiers SA3-SA6 is of no furtherrelevance to the understanding of the invention, the sense amplifiersSA3-SA6 are merely illustrated as a black box in FIG. 1. Depending ontheir position within the regular configuration of memory devices,however, these sense amplifiers SA3-SA6 are contact-connected on bothsides or one side by the bit lines BL3, {overscore (BL)}3 and BL4,{overscore (BL)}4 and preferably have circuitry analogous to the senseamplifiers SA1 or SA2. The connection scheme shown in FIG. 1, the senseamplifiers SA1-SA6 being connected to one another alternately via theeight bit lines BL1-BL4 and {overscore (BL)}1-{overscore (BL)}4 combinedin pairs, continues in the bit line direction, so that in each caseevery second sense amplifier SA of a series, in the bit line direction,is contact-connected in each case by the same bit line pairBL1/{overscore (BL)}1-BL4/{overscore (BL)}4.

[0043] At the input regions of the bit lines BL1, {overscore (BL)}1,BL2, {overscore (BL)}2, each sense amplifier SA1, SA2 in each case has atransistor switch TR1-TR8 (isolating transistor) which is formed as ann-channel field-effect transistor (N-FET) and isolates the senseamplifier SA1, SA2 from the respective bit line BL1, {overscore (BL)}1,BL2, {overscore (BL)}2. The transistor switches TR1, TR2, TR5, TR6 ofone side of the sense amplifiers SA1, SA2 are driven via a firstselection line AL1 and the transistor switches TR3, TR4, TR7, TR8 of theother side of the sense amplifiers SA1, SA2 are driven via secondselection line AL2, so that, during a read/write operation, the senseamplifiers SA1, SA2 can be selectively connected to the memory cells ofone side or the other side of the bit lines BL1, {overscore (BL)}1, BL2,{overscore (BL)}2.

[0044] On account of the high integration density and the resultantsmall dimensions of the N-FET transistor switches TR1-TR8 in the senseamplifiers SA1, SA2, the input regions of the sense amplifiers SA1, SA2are at relatively high resistance (several kV) even in the activatedstate.

[0045] Each of the memory cells MC, {overscore (MC)} of the memoryconfiguration has a charge corresponding to one of the two logic dataunits “0” or “1”, the charge having been written to the memory cell MC,{overscore (MC)} beforehand via the respective bit line BL, {overscore(BL)}.

[0046] During a read-out operation of a memory cell MC, {overscore(MC)}, the transfer transistor of the memory cell MC, {overscore (MC)}is turned on by activation of the corresponding word line WL, {overscore(WL)}, so that the potential of the bit line BL, {overscore (BL)} whichmakes contact with the memory cell MC, {overscore (MC)} is altered froman equalization potential—generated by a short circuit with thecomplementary bit line {overscore (BL)}, BL—in accordance with therespective charge state of the memory cell MC, {overscore (MC)}.

[0047] Since the capacitance of the bit line BL, {overscore (BL)} isseveral times greater than the capacitance of an individual memory cellMC, {overscore (MC)}, the potential of the bit line BL, {overscore (BL)}varies only slightly on account of the charge of the memory cell MC,{overscore (MC)}, especially as this charge originally contained in thememory cell MC, {overscore (MC)} is reduced by internal interferingfactors such as e.g. leakage currents within the memory cell MC,{overscore (MC)}. The potential difference—generated by the charge ofthe memory cell MC, {overscore (MC)}—between the bit lines BL,{overscore (BL)} of a bit line pair therefore turns out to be relativelysmall, and can be altered by capacitive coupling-in of signals ofadjacent bit lines at the instant of the read operation in such a waythat it is misinterpreted by the sense amplifier SA, which leads to aread error.

[0048] In order to reduce the coupling noise, it is possible to reducethe coupling capacitances of the bit lines BL1-BL4, {overscore(BL)}1-{overscore (BL)}4 between the sense amplifiers SA1-SA6 bymutually crossing the bit lines BL1-BL4, {overscore (BL)}1-{overscore(BL)}4.

[0049] The evaluation of the potential difference of a bit line BL andits reference bit line {overscore (BL)} generally takes place in a veryshort time. The sense amplifier SA, which is usually formed as asymmetrical sensor flip-flop F in a DRAM memory, reacts directly to thepotential difference between the two bit lines BL, {overscore (BL)} andpulls the bit lines BL, {overscore (BL)}, in accordance with theirdifference, to the ground potential or the full bit line potential. Onaccount of this property of the sense amplifier SA and the transistorswitches TR having a high impedance in its input regions, the senseamplifier SA “perceives” the coupling noise on the bit lines BL,{overscore (BL)} to a much lesser extent than the coupling noise on itsinternal signal lines SL, {overscore (SL)}. Therefore, the senseamplifier SA can practically be considered as decoupled from the bitlines BL, {overscore (BL)} for the short time interval of theevaluation.

[0050] It is an aim of the invention, therefore, to reduce theinterfering coupling noise within the sense amplifier SA1, which iscaused by the coupling-in of the potentials of the adjacent bit linesBL2, {overscore (BL)}2, and thus to significantly improve thesignal/interference signal ratio of the sense amplifier SA1. For thispurpose, the signal lines SL1, {overscore (SL)}1 have, within the senseamplifier SA1, a crossover 10 according to the invention. In this case,this crossover region 10 is essentially arranged in the capacitivecenter of the sense amplifier SA1, so that the changes—caused e.g. bythe coupling-in of the electrical potential of an adjacent signal lineSL2, {overscore (SL)}2—in the potential difference between the signallines SL1, {overscore (SL)}1, on the two partial regions of the signallines SL1, {overscore (SL)}1 that are formed by the crossover region 10,mutually cancel one another out.

[0051] Since the capacitance between the signal lines SL1, {overscore(SL)}1, SL2, {overscore (SL)}2 behaves reciprocally with respect totheir distance and the signal line pairs SL1, {overscore (SL)}1, SL2,{overscore (SL)}2 that are adjacent in one plane mutually screen oneanother, it generally suffices to provide a crossover 10 according tothe invention of the associated signal lines SL, {overscore (SL)} onlyin the case of every second sense amplifier SA in the word linedirection. As is shown in FIG. 1, the sense amplifier SA2 therefore hasno crossover 10 of its signal lines SL2, {overscore (SL)}2. Thisconfiguration of crossed signal lines SL1, {overscore (SL)}1 andnon-crossed signal lines SL2, {overscore (SL)}2 within the senseamplifiers SA1 and SA2 continues systematically in the word linedirection, so that only every second sense amplifier SA has a crossedsignal line pair SL, {overscore (SL)}.

[0052]FIG. 2 shows, by way of example, the internal construction of thetwo sense amplifiers SA1, SA2 from FIG. 1. In this case, the senseamplifier SA2 is configured as a bistable multivibrator (latchflip-flop) that is contact-connected on both sides and is known per se,the two signal lines SL2, {overscore (SL)}2 running parallel to oneanother within the sense amplifier SA2. Since the sense amplifier SA1 isessentially configured like the sense amplifier SA2 and differs from thelatter only by virtue of the invention's crossover of the signal linesSL1, {overscore (SL)}1, only the sense amplifier SA2 is explained inmore detail in the further course of the functional description of thesense amplifiers SA1, SA2.

[0053] The sense amplifier SA2 has a virtually symmetrical constructionand essentially includes four transistor switches TR5-TR8 which form theinput regions of the bit lines BL2, {overscore (BL)}2 and arecontact-connected in pairs by the selection lines AL1, AL2, and anevaluation device F2 which is configured as a symmetrical flip-flopcircuit and is arranged in a central region of the sense amplifier SA2between two signal lines SL2, {overscore (SL)}2 running parallel to oneanother. As shown in FIG. 2, this evaluation device F2 is subdividedinto two partial regions F2 _(n) and F2 _(p), which are connected to oneanother via the signal lines SL2, {overscore (SL)}2. In this case, onepartial region F2 _(n) has a first and a second n-channel MOStransistor, whose source electrodes are connected to a low supplypotential (e.g. ground potential) of the memory device via a negativesense line NS and further elements (not illustrated here), while theother partial region F2 _(p) has a first and a second p-channel MOStransistor, whose source electrodes are connected to a high supplypotential via a positive sense line PS and further elements (likewisenot illustrated here). In both partial regions F2 _(n), F2 _(p), in eachcase the drain electrode of the first MOS transistor and the gateelectrode of the second MOS transistor make contact with one of thesignal lines SL2, {overscore (SL)}2 and the drain electrode of thesecond MOS transistor and the gate electrode of the first MOS transistormake contact with the other of the signal lines SL2, {overscore (SL)}2.

[0054] The bistable multivibrator F2 of the sense amplifier SA2 has twostable states, the MOS transistors of the respective partial regions F2_(n), F2 _(p) being turned on in such a way that the high supplypotential is present on one of the two signal lines SL2, {overscore(SL)}2 and the low supply potential is present on the other of the twosignal lines SL2, {overscore (SL)}2 of the sense amplifier SA2.

[0055] In this case, the states of the bistable multivibrator whichresult from the potential difference of the bit line pair BL2,{overscore (BL)}2 are initiated by activation of the PS and NS lines.The multivibrator then moves independently into one or the other stableend state.

[0056] If e.g. the potential difference between the signal lines SL2,{overscore (SL)}2, on account of the charge of a memory cell MC2,{overscore (MC)}2 which acts on the bit lines BL2, {overscore (BL)}2, ispolarized such that the signal line SL2 is more positive than the signalline {overscore (SL)}2, then the n-channel MOS transistors FT6 and FT7move in the direction of increasing conductivity and the p-channel MOStransistors FT5 and FT8 in the direction of increasing blocking, so thatthe signal line SL2 is pulled to the positive supply potential and thesignal line {overscore (SL)}2 to the negative supply potential (orground potential). The opposite state is established in the event of anopposite initial polarity of the two signal lines SL2, {overscore(SL)}2, the signal line SL2 being pulled to the negative supplypotential (or ground potential) and the signal line {overscore (SL)}2 tothe positive supply potential. In this case, the circuit is latched inthe state reached on account of the mutual coupling of the transistorsFT5-FT8, so that even relatively large interference signals which act onthe sense amplifier on account of instances of coupling-in can no longeralter the pulled-apart potential difference on the two signal lines SL2,{overscore (SL)}2.

[0057] Outside the input regions TR5-TR8, the sense amplifier SA2 ineach case has a precharge circuit EQ3, EQ4 on each side of the bit linesBL2, {overscore (BL)}2, the circuit being controlled via a prechargeselect line EQL1, EQL2. These precharge circuits EQ3, EQ4 produce apotential equalization of the two bit lines BL2, {overscore (BL)}2before a read-out operation by virtue of the bit lines BL2, {overscore(BL)}2 being short-circuited by the precharge circuits EQ3, EQ4, whichare activated via the lines EQL1, EQL2, and being brought to anequalization potential V_(BLEQ).

[0058] Between the right-hand partial region F2p of the evaluationcircuit F2 and the input regions TR7, TR8, the sense amplifierfurthermore has a column select gate circuit CS2 which can be turned onvia a column select line CSL and connects a first data line LDQ to thefirst signal line SL2 and a second data line {overscore (LDQ)} to thesecond signal line {overscore (SL)}2, the data lines LDQ, {overscore(LDQ)} leading to the message source and message sink, respectively.

[0059] The sense amplifier SA1 has an internal construction analogous tothe sense amplifier SA2. In the capacitive mid point of the senseamplifier SA1, which, on account of the symmetry of the circuit of thesense amplifier 10, is situated approximately in the central region ofthe circuit, the two signal lines SL1, {overscore (SL)}1, that runessentially parallel to one another have, however, a crossover 10 withone another according to the invention.

[0060] Since the signal lines SL, {overscore (SL)} are electricallyisolated from one another in the case of deactivated sense lines NS, PS,they each represent, in a simplified mode of consideration, an electrodeof a capacitance arranged perpendicular to the bit line direction. Thetwo partial regions of the circuit of the sense amplifier SA1 that areformed by the crossover point therefore act like two parallel-arrangedcapacitors whose electrodes are cross-connected to one another.

[0061] The potential differences that are coupled into both capacitorsof the sense amplifier SA1 are identical in terms of magnitude, but havedifferent signs, so that they mutually cancel one another out.

[0062] The position of the crossover point can vary depending on thelayout of the evaluation circuit SA1. What is crucial in this case isthat the crossover point is arranged in the capacitive mid point, forthe determination of which not only the signal lines SL1, {overscore(SL)}1 but also the capacitive properties of the entire evaluationcircuit SA1, that is to say also of the components and their leads, haveto be taken into account. Furthermore, depending on the layout, the twosignal lines SL, {overscore (SL)} can also cross one another multiplywithin the evaluation circuit SA. In this case, the crossover points arearranged in such a way that the capacitances of the partial regions ofthe evaluation circuit SA that are formed by the crossover pointsmutually compensate for one another.

[0063] A crossover 10 according to the invention of the signal lines SL,{overscore (SL)} in the capacitive mid point of an evaluation circuit SAminimizes the coupling-in of interference signals of adjacent bit linesBL, {overscore (BL)}. In this case, it suffices to cross the signallines SL, {overscore (SL)} in every second evaluation circuit SA in theword line direction.

[0064] The features of the invention that are disclosed in the abovedescription, the claims and the drawings may be essential bothindividually and in any desired combination for the realization of theinvention in its various embodiments.

We claim:
 1. A memory device, comprising: a memory cell; an evaluationcircuit; a reference line connected to said evaluation circuit a bitline defining a bit line direction; said memory cell being connected tosaid evaluation circuit via said bit line; a first signal line, said bitline being connected, within said evaluation circuit, to said firstsignal line; a second signal line, said reference line being connected,within said evaluation circuit, to said second signal line; said bitline and said reference line having respective electrical potentials,said evaluation circuit amplifying a difference between the respectiveelectrical potentials of said bit line and said reference line; and saidfirst and second signal lines having a crossover region within saidevaluation circuit, said crossover region forming sections along the bitline direction in said evaluation circuit, said sections along the bitline direction having mutually substantially corresponding capacitances.2. The memory device according to claim 1, wherein: said first andsecond signal lines extend through said evaluation circuit; saidevaluation circuit has two sides, said bit line and said reference linemake contact with a respective one of said first signal line and saidsecond signal line at said two sides of said evaluation circuit; andsaid bit line is connected to said memory cell on a first one of saidtwo sides of said evaluation circuit and is connected to a furthermemory cell on a second one of said two sides of said evaluationcircuit.
 3. The memory device according to claim 1, wherein saidevaluation circuit has a high-resistance input region for each of saidbit line and said reference line.
 4. The memory device according toclaim 1, wherein: said evaluation circuit is an amplifier selected fromthe group consisting of a measurement amplifier and a sense amplifier;and said amplifier amplifies the respective electrical potentials ofsaid bit line and of said reference line in accordance with thedifference between the respective electrical potentials such that therespective electrical potentials are amplified to two given potentialvalues.
 5. The memory device according to claim 1, including a furthermemory cell, said reference line being configured as a bit line for saidfurther memory cell.
 6. The memory device according to claim 1, whereinsaid memory cell is a dynamic random access memory cell.
 7. The memorydevice according to claim 1, wherein said sections formed by saidcrossover region along the bit line direction have mutually compensatingcapacitances.
 8. The memory device according to claim 1, including: aplurality of evaluation circuits disposed as a matrix configuration; aplurality of first and second signal lines; a word line defining a wordline direction; a plurality of memory cells disposed between two of saidevaluation circuits along said bit line; and said evaluation circuitsbeing configured such that, in the word line direction, respective onesof said first and second signal lines form respective crossover regionsin every other one of said evaluation circuits.